//--------------------------------------------------------------------------------------------
//   : 
//      Component name  : fpmul
//      Author          : 
//      Company         : 
//
//      Description     : 
//
//
//--------------------------------------------------------------------------------------------


module FPmul(FP_A, FP_B, clk, FP_Z,IVLD,OVLD);
   input [31:0]  FP_A;
   input [31:0]  FP_B;
   input         clk;
   output [31:0] FP_Z;
   input         IVLD;
   output        OVLD;
   wire          OVLD;
   
   
   wire [7:0]    A_EXP;
   wire [31:0]   A_SIG;
   wire [7:0]    B_EXP;
   wire [31:0]   B_SIG;
   wire [7:0]    EXP_in;
   wire          EXP_neg;
   wire          EXP_neg_stage2;
   wire [7:0]    EXP_out_round;
   wire          EXP_pos;
   wire          EXP_pos_stage2;
   wire          SIGN_out;
   wire          SIGN_out_stage1;
   wire          SIGN_out_stage2;
   wire [27:0]   SIG_in;
   wire [27:0]   SIG_out_round;
   wire          isINF_stage1;
   wire          isINF_stage2;
   wire          isINF_tab;
   wire          isNaN;
   wire          isNaN_stage1;
   wire          isNaN_stage2;
   wire          isZ_tab;
   wire          isZ_tab_stage1;
   wire          isZ_tab_stage2;
   
   
   FPmul_stage1 I1(/*AUTOINST*/
		   // Outputs
		   .A_EXP		(A_EXP[7:0]),
		   .A_SIG		(A_SIG[31:0]),
		   .B_EXP		(B_EXP[7:0]),
		   .B_SIG		(B_SIG[31:0]),
		   .SIGN_out_stage1	(SIGN_out_stage1),
		   .isINF_stage1	(isINF_stage1),
		   .isNaN_stage1	(isNaN_stage1),
		   .isZ_tab_stage1	(isZ_tab_stage1),
		   // Inputs
		   .FP_A		(FP_A[31:0]),
		   .FP_B		(FP_B[31:0]),
		   .clk			(clk));
   
   FPmul_stage2 I2(/*AUTOINST*/
		   // Outputs
		   .EXP_in		(EXP_in[7:0]),
		   .EXP_neg_stage2	(EXP_neg_stage2),
		   .EXP_pos_stage2	(EXP_pos_stage2),
		   .SIGN_out_stage2	(SIGN_out_stage2),
		   .SIG_in		(SIG_in[27:0]),
		   .isINF_stage2	(isINF_stage2),
		   .isNaN_stage2	(isNaN_stage2),
		   .isZ_tab_stage2	(isZ_tab_stage2),
		   // Inputs
		   .A_EXP		(A_EXP[7:0]),
		   .A_SIG		(A_SIG[31:0]),
		   .B_EXP		(B_EXP[7:0]),
		   .B_SIG		(B_SIG[31:0]),
		   .SIGN_out_stage1	(SIGN_out_stage1),
		   .clk			(clk),
		   .isINF_stage1	(isINF_stage1),
		   .isNaN_stage1	(isNaN_stage1),
		   .isZ_tab_stage1	(isZ_tab_stage1));
   
   FPmul_stage3 I3(/*AUTOINST*/
		   // Outputs
		   .EXP_neg		(EXP_neg),
		   .EXP_out_round	(EXP_out_round[7:0]),
		   .EXP_pos		(EXP_pos),
		   .SIGN_out		(SIGN_out),
		   .SIG_out_round	(SIG_out_round[27:0]),
		   .isINF_tab		(isINF_tab),
		   .isNaN		(isNaN),
		   .isZ_tab		(isZ_tab),
		   // Inputs
		   .EXP_in		(EXP_in[7:0]),
		   .EXP_neg_stage2	(EXP_neg_stage2),
		   .EXP_pos_stage2	(EXP_pos_stage2),
		   .SIGN_out_stage2	(SIGN_out_stage2),
		   .SIG_in		(SIG_in[27:0]),
		   .clk			(clk),
		   .isINF_stage2	(isINF_stage2),
		   .isNaN_stage2	(isNaN_stage2),
		   .isZ_tab_stage2	(isZ_tab_stage2));
   
   FPmul_stage4 I4(/*AUTOINST*/
		   // Outputs
		   .FP_Z		(FP_Z[31:0]),
		   // Inputs
		   .EXP_neg		(EXP_neg),
		   .EXP_out_round	(EXP_out_round[7:0]),
		   .EXP_pos		(EXP_pos),
		   .SIGN_out		(SIGN_out),
		   .SIG_out_round	(SIG_out_round[27:0]),
		   .clk			(clk),
		   .isINF_tab		(isINF_tab),
		   .isNaN		(isNaN),
		   .isZ_tab		(isZ_tab));
   


reg    [7:0]      ivld_dly  = 'd0 ;
always @ (posedge clk )
begin
	ivld_dly <= {ivld_dly[6:0],IVLD};
end
assign   OVLD = ivld_dly[3] ;




endmodule
